Although applicable in principle to any desired integrated circuits, the present invention and also the problem area on which it is based are explained with regard to chips with integrated circuits in silicon technology.
Known CSP (Chip Size Package) or WLP (Wafer Level Package) solutions for connecting an integrated circuit to a substrate have reliability problems in the event of temperature changes particularly in the case of large circuit arrangements, to be precise particularly in the context of ever decreasing distances between substrate and packaged chip. The different thermal expansion coefficients of packaged circuit arrangement and substrate give rise to different linear expansions of the two components during the temperature changes.
In the case of chip size packages and wafer level packages, essentially two types of connecting structures between the chip and the substrate have been disclosed heretofore.
The first customary solution for connecting an integrated circuit to a substrate is the use of ball grid arrays with rigid solder balls or bumps for mechanical connection with the additional use of an underfill in order to increase the stability. In the case of this solution, the mismatch of the thermal properties of the chip and of the substrate, in particular of the thermal expansion coefficient, leads to major reliability risks. The solder balls may be sheared away in the event of temperature changes. This considerably restricts the reliability, particularly in the case of large chips.
In order to prevent such undesirable defects, various types of interposer layers have been developed, which serve as stress buffers between the chip having a low thermal expansion coefficient and the substrate having a highs thermal expansion coefficient. Such solutions increase the height of the construction, the number of connections and at least the costs.
FIG. 4 shows a diagrammatic view of a part of an interposer-type circuit arrangement for elucidating the problem area on which the invention is based.
In FIG. 4, reference symbol 100 designates a circuit substrate, for example in the form of a module board. Reference symbol la designates in combinative fashion a package of an integrated circuit, which is a chip 5 in the present case. The chip 5 has contact pads 6, at which electrical connections of the circuit situated therein are routed toward the outside. An interposer 15 is applied on the front side VS of the chip 5 by means of an adhesive layer 10, which interposer has, in the center, a feedthrough through which leads 7 are routed in a manner sealed by an adhesive 8, which are connected to the contact pads 6 at one of their ends and to connection regions 140 at their other end, the latter being provided on the connection side AS of the package 1a. The connection regions 140 are connected to a rewiring having a plurality of connection regions 50 which are provided for connection to a corresponding number of connection regions 110 on the circuit substrate 100.
This mechanical and electrical connection is realized by corresponding solder balls 30 between the connection regions 110, 150, an underfill agent 50 in the form of an adhesive additionally being introduced between circuit substrate 100 and interposer 15.
An encapsulation 20, for example made of nontransparent epoxy resin, is provided on the rear side of the chip 5. The broken lines in FIG. 4 designate a flexure influence V on account of thermal mismatches, which has the effect that, in the case of a geometry of this type, the edge regions, in particular, are subject to a high stress ST. This stress ST is ultimately the reason why the outer solder balls are often sheared away or torn away in the event of temperature changes.
FIG. 5 shows a diagrammatic view of a part of a chip-size-type circuit arrangement for elucidating the problem area on which the invention is based.
In contrast to the arrangement in accordance with FIG. 4, no interposer is provided in the case of the arrangement in accordance with FIG. 5. Rather, a dielectric layer 25 is situated there on the front side VS of the chip 5, on which dielectric layer there are provided connection regions 150 connected to the contact pads 6 via the rewiring. Analogously to the example according to FIG. 4, solder balls 30 are provided, which provide a mechanical and electrical connection between the package 1b with the chip 5 and the circuit substrate 100. In order to provide an undesirable flowing away of solder, a solder resist layer of 120 is furthermore provided on the connection side AS, which layer has the effect that the solder balls 30 are maintained at the locations provided and do not flow away. In this example, too, an underfill layer 50 in the form of an adhesive layer is provided for stabilization.
A further solution for connecting an integrated circuit to a substrate is the use of elastic elevations, which is disclosed in WO 00/79589 A1. The latter discloses an electronic component having flexible raised portions made of an insulating material on a surface, an electrical contact being arranged on the flexible elevation and a conduction path being arranged on the surface or in the interior of the flexible elevation between the electrical contact and the electronic circuit. The advantage of this solution is a smaller construction height, a higher reliability and lower costs. In this connection, it is known to solder or adhesively bond the elastic contact elements onto the substrate.
One disadvantage of this solution is that the dissipation of heat from the integrated circuit is significantly poorer in the case of flexible plastic contact elements than in the case of solder balls. A further disadvantage resides in poorer mechanical fixing.